export PrjDIR=../..
export PrjRTL=${PrjDIR}/design
export PrjSIM=..
export TB_DIR=../testbench


TESTCASE?=apbuart_config_test

SCALE=1ns
FILE = testname.f
TEST_NAMES =`cat $(FILE)`


DUT_FILELIST= -f ${PrjRTL}/rtl.f
TB_FILELIST= -f ${TB_DIR}/filelist/tb_list.f

all: comp sim

comp:
	vcs -full64 -kdb -sverilog -debug_access+all -debug_region=cell+lib \
	-timescale=1ns/1ps -ntb_opts uvm-1.2 +notimingcheck -l vcs_compile.log \
	${DUT_FILELIST} ${TB_FILELIST} -top tb_top

sim:
	mkdir -p ${TESTCASE}_sim_dir
	cd ${TESTCASE}_sim_dir; ../simv -l sim_${TESTCASE}.log +UVM_TIMEOUT=900000000 +UVM_TESTNAME=${TESTCASE}


verdik:
	verdi -elab simv.daidir/kdb.elab++ &

clean:
	rm -rf csrc DVEfiles urgReport simv.vdb simv simv.daidir ucli.key vc_hdrs.h vcs_compile.log 

cleanall: clean
	rm -rf *_sim_dir novas.conf novas.rc verdiLog

